ADRES
IMEC’s multi-threaded ADRES processor architecture ready for licensing
Leuven, Belgium – October 5, 2009 – Today, IMEC unveils the second generation of its ADRES processor architecture (architecture for dynamically reconfigurable embedded systems). ADRES now supports multithreading, and has doubled its performance and energy efficiency compared to the first ADRES generation. This positions ADRES as a building block for future 4G devices. ADRES can [...]
IMEC unveils tools to speed up design of energy-efficient multi-processor SoC platforms
IMEC announced The IMEC MPSoC technology provides solutions by focusing on design-time application mapping. The technology’s two main threads offer support for fast parallelization (with the Multi-processor Parallelization Assistant tool) and support for memory hierarchy optimizations (with the Memory Hierarchy tool).
IMEC’s tools, methods, and associated services have a proven industrial strength. They have been used [...]